MC68HC908AS32A Datasheet, PDF (138/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

External Interrupt Module (IRQ)
FROM RESET
YES
I BIT SET?
NO
INTERRUPT?
NO
YES
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
YES
INSTRUCTION?
NO
RTI
YES
INSTRUCTION?
NO
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
Figure 10-3. IRQ Interrupt Flowchart
The vector fetch or software clear and the return of the IRQ pin to a high level can occur in any order. The
interrupt request remains pending as long as the IRQ pin is low. A reset will clear the latch and the MODE
control bit; thereby, clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge sensitive only. With MODE clear, a vector fetch or
software clear immediately clears the IRQ latch.
The IRQF bit in the ISCR register can be used to check for pending interrupts. The IRQF bit is not affected
by the IMASK bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
MC68HC908AS32A Data Sheet, Rev. 2.0
138
Freescale Semiconductor