MC68HC908AS32A Datasheet, PDF (180/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Communications Interface (SCI)
Table 14-5. Character Format Selection
Control Bits
M PEN and PTY
0
0X
1
0X
0
10
0
11
1
10
1
11
Start Bits
1
1
1
1
1
1
Character Format
Data Bits Parity Stop Bits
8
None
1
9
None
1
7
Even
1
7
Odd
1
8
Even
1
8
Odd
1
Character Length
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
14.8.2 SCI Control Register 2
SCI control register 2:
• Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt requests
– Enables the TC bit to generate transmitter CPU interrupt requests
– Enables the SCRF bit to generate receiver CPU interrupt requests
– Enables the IDLE bit to generate receiver CPU interrupt requests
• Enables the transmitter
• Enables the receiver
• Enables SCI wakeup
• Transmits SCI break characters
Address: $0014
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 14-10. SCI Control Register 2 (SCC2)
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Setting
the SCTIE bit in SCC3 enables the SCTE bit to generate CPU interrupt requests. Reset clears the
SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears
the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
MC68HC908AS32A Data Sheet, Rev. 2.0
180
Freescale Semiconductor