MC68HC908AS32A Datasheet, PDF (137/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

ACK
VECTOR
FETCH
DECODER
IRQ
V_DD
CLR
D
Q
CK
IRQ
LATCH
IRQ Pin
SYNCHRO-
NIZER
IMASK
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQF
IRQ
INTERRUPT
REQUEST
MODE
HIGH
VOLTAGE
DETECT
Figure 10-2. IRQ Block Diagram
TO MODE
SELECT
LOGIC
When set, the IMASK bit in the ISCR masks all external interrupt requests. A latched interrupt request is
not presented to the interrupt priority logic unless the corresponding IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. Refer to Figure
10-3.
10.4 IRQ Pin
A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software
clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge sensitive and low-level sensitive. With MODE set,
both of the following actions must occur to clear the IRQ latch:
• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a 1 to the ACK bit in
the interrupt status and control register (ISCR). The ACK bit is useful in applications that poll the
IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit can also prevent
spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ
pin. A falling edge on IRQ that occurs after writing to the ACK bit latches another interrupt request.
If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address
at locations $FFFA and $FFFB.
• Return of the IRQ pin to a high level — As long as the IRQ pin is low, the IRQ1 latch remains set.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
137