MC68HC908AS32A Datasheet, PDF (210/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface (SPI)
16.5.2 Transmission Format When CPHA = 0
Figure 16-4 shows an SPI transmission in which CPHA (SPCR) is 0. The figure should not be used as a
replacement for data sheet parametric information. Two waveforms are shown for SCK: one for CPOL = 0
and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the
serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI
signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives
its MISO output only when its slave select input (SS) is low, so that only the selected slave drives to the
master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master
must be high or must be reconfigured as general-purpose I/O not affecting the SPI (see 16.6.2 Mode Fault
Error). When CPHA = 0, the first SPSCK edge is the MSB capture strobe. Therefore, the slave must begin
driving its data before the first SPSCK edge, and a falling edge on the SS pin is used to start the
transmission. The SS pin must be toggled high and then low again between each byte transmitted.
SCK CYCLE #
FOR REFERENCE
SCK CPOL = 0
SCK CPOL = 1
MOSI
FROM MASTER
MISO
FROM SLAVE
SS TO SLAVE
CAPTURE STROBE
1
2
3
4
5
6
7
8
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
Figure 16-4. Transmission Format (CPHA = 0)
MC68HC908AS32A Data Sheet, Rev. 2.0
210
Freescale Semiconductor