MC68HC908AS32A Datasheet, PDF (240/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM)
Register Name and Address
TSC0 — $0026
Read:
Write:
Bit 7
CH0F
0
6
CH0IE
5
MS0B
4
MS0A
3
ELS0B
2
ELS0A
1
Bit 0
TOV0 CH0MAX
Reset: 0
0
0
0
0
0
0
0
Register Name and Address
TSC1 — $0029
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH1F
0
CH1IE
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset: 0
0
0
0
0
0
0
0
Register Name and Address
Bit 7
6
Read: CH2F
Write: 0
CH2IE
Reset: 0
0
Register Name and Address
TSC2 — $002C
5
4
MS2B MS2A
0
0
TSC3 — $002F
3
ELS2B
0
2
ELS2A
0
1
Bit 0
TOV2 CH2MAX
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH3F
0
CH3IE
MS3A ELS3B ELS3A TOV3 CH3MAX
Write: 0
Reset: 0
0
0
0
0
0
0
0
Register Name and Address
TSC4 — $0032
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
CH4F
0
0
CH4IE
0
MS4B
0
MS4A
0
ELS4B
0
ELS4A
0
TOV4 CH4MAX
0
0
Register Name and Address
TSC5 — $0035
Bit 7
6
5
4
Read: CH5F
0
CH5IE
MS5A
Write: 0
Reset: 0
0
0
0
= Unimplemented
3
ELS5B
0
2
ELS5A
0
1
Bit 0
TOV5 CH5MAX
0
0
Figure 17-7. TIM Channel Status and Control Registers (TSC0–TSC5)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
When CHxIE = 1, clear CHxF by reading TIM channel x status and control register with CHxF set and
then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete,
then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent
clearing of CHxF.
MC68HC908AS32A Data Sheet, Rev. 2.0
240
Freescale Semiconductor