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MC68HC908AS32A Datasheet, PDF (262/280 Pages) Freescale Semiconductor, Inc – Microcontrollers
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Electrical Specifications
19.6 Control Timing
Characteristic(1)
Symbol
Min
Max
Unit
Bus operating frequency (4.5–5.5 V — VDD only)
RST pulse width low
IRQ interrupt pulse width low (edge-triggered)
IRQ interrupt pulse period
16-bit timer(2)
Input capture pulse width(3)
Input capture period
fBus
—
8.4
tRL
1.5
—
tILHI
1.5
—
tILIL
Note 4
—
tTH, tTL
2
—
tTLTL
Note(4)
—
MHz
tcyc
tcyc
tcyc
tcyc
1. VDD = 5.0 Vdc ± 0.5 V, VSS = 0 Vdc, TA = –40°C to TA(MAX), unless otherwise noted.
2. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
3. Refer to Table 17-2. Mode, Edge, and Level Selection.
4. The minimum period tTLTL or tILIL should not be less than the number of cycles it takes to execute the capture interrupt
service routine plus TBD tcyc.
19.7 Analog-to-Digital Converter (ADC) Characteristics
Characteristic
Min
Max
Unit
Comments
Resolution
8
8
Bits
Absolute accuracy
(VREFL = 0 V, VDDA/VDDAREF = VREFH = 5 V ± 0.5 V)
–1
+1
LSB
Includes quantization
Conversion range(1)
Power-up time
VREFL
16
VREFH
17
V
VREFL = VSSA
µs
Conversion time period
Input leakage(2) (ports B and D)
–1
1
µA
Conversion time
16
17
ADC clock
cycles
Includes sampling time
Monotonicity
Inherent within total error
Zero input reading
Full-scale reading
00
01
Hex
FE
FF
Hex
VIn = VREFL
VIn = VREFH
Sample time(3)
5
—
ADC clock
cycles
Input capacitance
—
8
pF
Not tested
ADC internal clock
500 k
1.048 M
Hz
Tested only at 1 MHz
Analog input voltage
VREFL
VREFH
V
1. VDD = 5.0 Vdc ± 0.5 V, VSS = 0 Vdc, VDDA/VDDAREF = 5.0 Vdc ± 0.5 V, VSSA = 0 Vdc, VREFH = 5.0 Vdc ± 0.5 V
2. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
3. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
MC68HC908AS32A Data Sheet, Rev. 2.0
262
Freescale Semiconductor
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