MC68HC908AS32A Datasheet, PDF (101/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
• Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. See 5.3.3 Base Clock Selector Circuit for more information. The PLL is
automatically in tracking mode when it’s not in acquisition mode or when the ACQ bit is set.
5.3.2.3 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. See 5.5.2 PLL
Bandwidth Control Register for more information. If PLL CPU interrupt requests are enabled, the software
can wait for a PLL CPU interrupt request and then check the LOCK bit. If CPU interrupts are disabled,
software can poll the LOCK bit continuously (during PLL startup, usually) or at periodic intervals. In either
case, when the LOCK bit is set, the VCO clock is safe to use as the source for the base clock. See 5.3.3
Base Clock Selector Circuit for more information. If the VCO is selected as the source for the base clock
and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate
action, depending on the application. See 5.6 Interrupts for more information.
These conditions apply when the PLL is in automatic bandwidth control mode:
• The ACQ bit (see 5.5.2 PLL Bandwidth Control Register) is a read-only indicator of the mode of the
filter. See 5.3.2.2 Acquisition and Tracking Modes for more information.
• The ACQ bit is set when the VCO frequency is within a certain tolerance, ∆_trk, and is cleared when
the VCO frequency is out of a certain tolerance, ∆_unt. See Chapter 19 Electrical Specifications for
more information.
• The LOCK bit is a read-only indicator of the locked state of the PLL.
• The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆_Lock, and is cleared
when the VCO frequency is out of a certain tolerance, ∆_UNL. See Chapter 19 Electrical
Specifications for more information.
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. See 5.5.1 PLL Control Register for more information.
The PLL also can operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
f_BUSMAX and require fast startup. The following conditions apply when in manual mode:
• ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ bit must be clear.
• Before entering tracking mode (ACQ = 1), software must wait a given time, t_ACQ (see Chapter 19
Electrical Specifications for more information), after turning on the PLL by setting PLLON in the PLL
control register (PCTL).
• Software must wait a given time, t_AL, after entering tracking mode before selecting the PLL as the
clock source to CGMOUT (BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
101