MC68HC908AS32A Datasheet, PDF (80/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller (BDLC)
240 µs
ACTIVE
(2) VALID BREAK SYMBOL
PASSIVE
e
Figure 4-11. J1850 VPW Received BREAK Symbol Times
4.4.5 Message Arbitration
Message arbitration on the J1850 bus is accomplished in a non-destructive manner, allowing the
message with the highest priority to be transmitted, while any transmitters which lose arbitration simply
stop transmitting and wait for an idle bus to begin transmitting again.
If the BDLC wants to transmit onto the J1850 bus, but detects that another message is in progress, it waits
until the bus is idle. However, if multiple nodes begin to transmit in the same synchronization window,
message arbitration will occur beginning with the first bit after the SOF symbol and will continue with each
bit thereafter.
The variable pulse width modulation (VPW) symbols and J1850 bus electrical characteristics are chosen
carefully so that a logic 0 (active or passive type) will always dominate over a logic 1 (active or passive
type) that is simultaneously transmitted. Hence, logic 0s are said to be dominant and logic 1s are said to
be recessive.
Whenever a node detects a dominant bit on BDRxD when it transmitted a recessive bit, the node loses
arbitration and immediately stops transmitting. This is known as bitwise arbitration.
Since a logic 0 dominates a logic 1, the message with the lowest value will have the highest priority and
will always win arbitration. For instance, a message with priority 000 will win arbitration over a message
with priority 011.
This method of arbitration will work no matter how many bits of priority encoding are contained in the
message.
During arbitration, or even throughout the transmitting message, when an opposite bit is detected,
transmission is stopped immediately unless it occurs on the 8th bit of a byte. In this case, the BDLC
automatically will append up to two extra logic 1 bits and then stop transmitting. These two extra bits will
be arbitrated normally and thus will not interfere with another message. The second logic 1 bit will not be
sent if the first loses arbitration. If the BDLC has lost arbitration to another valid message, then the two
extra logic 1s will not corrupt the current message. However, if the BDLC has lost arbitration due to noise
on the bus, then the two extra logic 1s will ensure that the current message will be detected and ignored
as a noise-corrupted message.
MC68HC908AS32A Data Sheet, Rev. 2.0
80
Freescale Semiconductor