MC68HC908AS32A Datasheet, PDF (66/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
ADICLK — ADC Input Clock Register Bit
ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC
clock. Reset selects CGMXCLK as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the
clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the
clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be
guaranteed. See 19.7 Analog-to-Digital Converter (ADC) Characteristics.
1 = Internal bus clock
0 = External clock (CGMXCLK)
1 MHz = ⎯^fX⎯^CL⎯^{K o}⎯^r ⎯^Bu⎯^s ⎯^Fr⎯^eq⎯^ue⎯^nc⎯^y
ADIV[2:0]
NOTE
During the conversion process, changing the ADC clock will result in an
incorrect conversion.
MC68HC908AS32A Data Sheet, Rev. 2.0
66
Freescale Semiconductor