MC68HC908AS32A Datasheet, PDF (75/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

BDLC MUX Interface
to the application software. Implementations of this BDLC design on silicon
have not been exposed to interframe separation rates faster than 320 µs in
practical application and have therefore previously not exhibited this
behavior. Ensuring that no nodes on the J1850 network transmit messages
at 300 µs (± 1 µs) IFS will avoid this missed message frame. In addition,
developing application software to robustly handle lost messages will
minimize application impact.
BREAK — Break
The BDLC cannot transmit a BREAK symbol.
If the BDLC is transmitting at the time a BREAK is detected, it treats the BREAK as if a transmission
error had occurred and halts transmission.
If the BDLC detects a BREAK symbol while receiving a message, it treats the BREAK as a reception
error and sets the invalid symbol flag in the BSVR, also ignoring the frame it was receiving. If while
receiving a message in 4X mode, the BDLC detects a BREAK symbol, it treats the BREAK as a
reception error, sets the invalid symbol flag, and exits 4X mode (for example, the RX4XE bit in BCR2
is cleared automatically). If bus control is required after the BREAK symbol is received and the IFS
time has elapsed, the programmer must resend the transmission byte using highest priority.
NOTE
The J1850 protocol BREAK symbol is not related to the HC08 break
module. Refer to 18.2 Break Module (BRK).
IDLE — Idle Bus
An idle condition exists on the bus during any passive period after expiration of the IFS period (for
instance, ≥ 300 µs). Any node sensing an idle bus condition can begin transmission immediately.
4.4.3 J1850 VPW Symbols
Huntsinger’s variable pulse width modulation (VPW) is an encoding technique in which each bit is defined
by the time between successive transitions and by the level of the bus between transitions (for instance,
active or passive). Active and passive bits are used alternately. This encoding technique is used to reduce
the number of bus transitions for a given bit rate.
Each logic 1 or logic 0 contains a single transition and can be at either the active or passive level and one
of two lengths, either 64 µs or 128 µs (t_NOM at 10.4 kbps baud rate), depending upon the encoding of the
previous bit. The start-of-frame (SOF), end-of-data (EOD), end-of-frame (EOF), and inter-frame
separation (IFS) symbols always will be encoded at an assigned level and length. See Figure 4-7.
Each message will begin with an SOF symbol an active symbol and, therefore, each data byte (including
the CRC byte) will begin with a passive bit, regardless of whether it is a 1 or a 0.
All VPW bit lengths stated in the following descriptions are typical values at a 10.4 kbps bit rate.
Logic 0
A logic 0 is defined as either:
– An active-to-passive transition followed by a passive period 64 µs in length, or
– A passive-to-active transition followed by an active period 128 µs in length
See Figure 4-7(a).
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
75