MC68HC908AS32A Datasheet, PDF (79/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

BDLC MUX Interface
200 µs
128 µs
64 µs
ACTIVE
(1) INVALID ACTIVE BIT
PASSIVE
a
ACTIVE
(2) VALID ACTIVE LOGIC 1
PASSIVE
a
b
ACTIVE
(3) VALID ACTIVE LOGIC 0
PASSIVE
ACTIVE
b
c
(4) VALID SOF SYMBOL
PASSIVE
c
d
Figure 4-10. J1850 VPW Received Active Symbol Times
Invalid Active Bit
In Figure 4-10(1), if the active-to-passive received transition beginning the next data bit (or symbol)
occurs between the passive-to-active transition beginning the current data bit (or symbol) and a, the
current bit would be invalid.
Valid Active Logic 1
In Figure 4-10(2), if the active-to-passive received transition beginning the next data bit (or symbol)
occurs between a and b, the current bit would be considered a logic 1.
Valid Active Logic 0
In Figure 4-10(3), if the active-to-passive received transition beginning the next data bit (or symbol)
occurs between b and c, the current bit would be considered a logic 0.
Valid SOF Symbol
In Figure 4-10(4), if the active-to-passive received transition beginning the next data bit (or symbol)
occurs between c and d, the current symbol would be considered a valid SOF symbol.
Valid BREAK Symbol
In Figure 4-11, if the next active-to-passive received transition does not occur until after e, the current
symbol will be considered a valid BREAK symbol. A BREAK symbol should be followed by a
start-of-frame (SOF) symbol beginning the next message to be transmitted onto the J1850 bus. See
4.4.2 J1850 Frame Format for BDLC response to BREAK symbols.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
79