MC68HC908AS32A Datasheet, PDF (135/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10
External Interrupt Module (IRQ)
10.1 Introduction
This section describes the non-maskable external interrupt (IRQ) input.
10.2 Features
Features include:
• Dedicated external interrupt pin (IRQ)
• Hysteresis buffer
• Programmable edge-only or edge- and level-interrupt sensitivity
• Automatic interrupt acknowledge
10.3 Functional Description
A falling edge applied to the external interrupt pin can latch a CPU interrupt request. Figure 10-2 shows
the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of
the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears
the latch that caused the vector fetch.
• Software clear — Software can clear an interrupt latch by writing to the appropriate acknowledge
bit in the interrupt status and control register (ISCR). Writing a 1 to the ACK bit clears the IRQ latch.
• Reset — A reset automatically clears both interrupt latches.
The external interrupt pin is falling-edge triggered and is software configurable to be both falling-edge and
low-level triggered. The MODE bit in the ISCR controls the triggering sensitivity of the IRQ pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software
clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both
of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to a high level
The vector fetch or software clear may occur before or after the interrupt pin returns to a high level. As
long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1
control bit, thereby clearing the interrupt even if the pin stays low.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
135