MC68HC908AS32A Datasheet, PDF (241/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

I/O Registers
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM
channel 0, TIM channel 2 and TIM channel 4 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts TCH1 pin to
general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and reverts TCH3 pin to
general-purpose I/O.
Setting MS4B disables the channel 5 status and control register and reverts TCH5 pin to
general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation. See Table 17-2.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin once PWM,
output compare mode or input capture mode is enabled. See Table 17-2. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to port E or port F and pin
PTEx/TCHx or pin PTFx/TCHx is available as a general-purpose I/O pin. However, channel x is at a
state determined by these bits and becomes transparent to the respective pin when PWM, input
capture mode or output compare operation mode is enabled. Table 17-2 shows how ELSxB and
ELSxA work. Reset clears the ELSxB and ELSxA bits.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
241