MC68HC908AS32A Datasheet, PDF (86/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller (BDLC)
NOTE
This device does not contain an on-board transceiver. This bit should be
programmed to a logic 0 for proper operation.
RXPOL — Receive Pin Polarity Bit
The receive pin polarity (RXPOL) bit is used to select the polarity of an incoming signal on the receive
pin. Some external analog transceivers invert the receive signal from the J1850 bus before feeding it
back to the digital receive pin.
1 = Select normal/true polarity; true non-inverted signal from the J1850 bus; for example, the
external transceiver does not invert the receive signal
0 = Select inverted polarity, where an external transceiver inverts the receive signal from the J1850
bus
B03–B00 — BARD Offset Bits
Table 4-2 shows the expected transceiver delay with respect to BARD offset values.
Table 4-2. BDLC Transceiver Delay
BARD Offset Bits
B0[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Corresponding Expected
Transceiver’s Delays (µs)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
4.6.2 BDLC Control Register 1
This register is used to configure and control the BDLC.
Address: $003C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
IMSG
CLKS
R1
R0
IE
WCM
Write:
R
R
Reset: 1
1
1
0
0
0
0
0
R = Reserved
Figure 4-17. BDLC Control Register 1 (BCR1)
MC68HC908AS32A Data Sheet, Rev. 2.0
86
Freescale Semiconductor