MC68HC908AS32A Datasheet, PDF (121/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

COP Control Register
8.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
8.3.7 COPD
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See
Chapter 6 Configuration Register (CONFIG1) for more information.
8.3.8 COPL
The COPL signal reflects the state of the COP rate select bit. (COPL) in the configuration register. See
Chapter 6 Configuration Register (CONFIG1) for more information.
8.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
LOW BYTE OF RESET VECTOR
CLEAR COP COUNTER
Unaffected by reset
Figure 8-2. COP Control Register (COPCTL)
8.5 Interrupts
The COP does not generate CPU interrupt requests.
8.6 Monitor Mode
The COP is disabled in monitor mode when V_TST is present on the IRQ pin or on the RST pin.
8.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
8.7.1 Wait Mode
The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout.
8.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
121