MC68HC908AS32A Datasheet, PDF (160/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output Ports
TCH[1:0] — Timer Channel I/O Bits
The PTE3/TACH1–PTE2/TACH0 pins are the TIM input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0 pins are timer channel
I/O pins or general-purpose I/O pins. See Chapter 17 Timer Interface Module (TIM).
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the TIM. However, the DDRE bits always
determine whether reading port E returns the states of the latches or the
states of the pins. See Table 13-5.
RxD — SCI Receive Data Input Bit
The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit (ENSCI) is
clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See
14.8.1 SCI Control Register 1.
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit (ENSCI) is
clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See
14.8.1 SCI Control Register 1.
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. See Table 13-5.
13.6.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input or an output. Writing a 1 to a
DDRE bit enables the output buffer for the corresponding port E pin; a 0 disables the output buffer.
Address: $000C
Bit 7
Read:
DDRE7
Write:
Reset: 0
6
DDRE6
0
5
DDRE5
0
4
DDRE4
0
3
DDRE3
0
2
DDRE2
0
1
DDRE1
0
Figure 13-14. Data Direction Register E (DDRE)
Bit 0
DDRE0
0
DDRE[7:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins
as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 13-15 shows the port E I/O logic.
MC68HC908AS32A Data Sheet, Rev. 2.0
160
Freescale Semiconductor