MC68HC908AS32A Datasheet, PDF (44/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory
B. If more than one valid EEPROM write occurs, the last address and data
will be latched overriding the previous address and data. Once data is
written to the desired address, do not read EEPROM locations other than
the written location. (Reading an EEPROM location returns the latched data
and causes the read address to be latched).
C. The EEPGM bit cannot be set if the EELAT bit is cleared or a non-valid
EEPROM address is latched. This is to ensure proper programming
sequence. Once EEPGM is set, do not read any EEPROM locations;
otherwise, the current program cycle will be unsuccessful. When EEPGM
is set, the on-board programming sequence will be activated.
D. The delay time for the EEPGM bit to be cleared in AUTO mode is less
than t_EEPGM. However, on other MCUs, this delay time may be different.
For forward compatibility, software should not make any dependency on
this delay time.
E. Any attempt to clear both EEPGM and EELAT bits with a single
instruction will only clear EEPGM. This is to allow time for removal of high
voltage from the EEPROM array.
2.8.1.8 EEPROM Erasing
The programmed state of an EEPROM bit is a 0. Erasing changes the state to a 1. Only EEPROM bytes
in the non-protected blocks and the EENVR register can be erased.
Use the following procedure to erase a byte, block, or the entire EEPROM array:
1. Configure EERAS1 and EERAS0 for byte, block, or bulk erase; set EELAT in EECR.^(A)
NOTE
If using the AUTO mode, also set the AUTO bit in step 1.
2. Byte erase — write any data to the desired address.^(B)
Block erase — write any data to an address within the desired block.^(B)
Bulk erase — write any data to an address within the array.^(B)
3. Set the EEPGM bit.^(C) Go to Step 7 if AUTO is set.
4. Wait for a time: t_EEBYTE for byte erase; t_EEBLOCK for block erase; t_EEBULK. for bulk erase.
5. Clear EEPGM bit.
6. Wait for a time, t_EEFPV, for the erasing voltage to fall. Go to Step 8.
7. Poll the EEPGM bit until it is cleared by the internal timer.^(D)
8. Clear EELAT bits.^(E)
NOTE
A. Setting the EELAT bit configures the address and data buses to latch
data for erasing the array. Only valid EEPROM addresses will be latched.
If EELAT is set, other writes to the EECR will be allowed after a valid
EEPROM write.
B. If more than one valid EEPROM write occurs, the last address and data
will be latched overriding the previous address and data. Once data is
written to the desired address, do not read EEPROM locations other than
MC68HC908AS32A Data Sheet, Rev. 2.0
44
Freescale Semiconductor