MC68HC908AS32A Datasheet, PDF (109/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Interrupts
Table 5-2. VCO Frequency Multiplier (N) Selection (Continued)
MUL7:MUL6:MUL5:MUL4
1101
1110
1111
VCO Frequency Multiplier (N)
13
14
15
NOTE
The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
VRS7–VRS4 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L, which controls the
hardware center-of-range frequency, f_VRS. (See 5.3.2.1 Circuits, 5.3.2.4 Programming the PLL, and
5.5.1 PLL Control Register for more information.) VRS7–VRS4 cannot be written when the PLLON bit
in the PLL control register (PCTL) is set. See 5.3.2.5 Special Programming Exceptions for more
information. A value of $0 in the VCO range select bits disables the PLL and clears the BCS bit in the
PCTL. (See 5.3.3 Base Clock Selector Circuit and 5.3.2.5 Special Programming Exceptions for more
information.) Reset initializes the bits to $6 to give a default range multiply value of 6.
NOTE
The VCO range select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1) and prevents selection of the
VCO clock as the source of the base clock (BCS = 1) if the VCO range
select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
5.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU
interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL)
enables CPU interrupt requests from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether
CPU interrupt requests are enabled or not. When the AUTO bit is clear, CPU interrupt requests from the
PLL are disabled and PLLF reads as 0.
Software should read the LOCK bit after a PLL CPU interrupt request to see if the request was due to an
entry into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two
can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO
clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency
sensitive, CPU interrupt requests should be disabled to prevent PLL interrupt service routines from
impeding software performance or from exceeding stack limitations.
NOTE
Software can select the CGMVCLK divided by two as the CGMOUT source
even if the PLL is not locked (LOCK = 0). Therefore, software should make
sure the PLL is locked before setting the BCS bit.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
109