MC68HC908AS32A Datasheet, PDF (189/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 15
System Integration Module (SIM)
15.1 Introduction
This section describes the system integration module (SIM), which supports up to 32 external and/or
internal interrupts. Together with the central processor unit (CPU), the SIM controls all MCU activities.The
SIM is a system state controller that coordinates CPU and exception timing.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
A block diagram of the SIM is shown in Figure 15-2.
Table 15-1 shows the internal signal names used in this section.
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
IAB
IDB
PORRST
IRST
R/W
Table 15-1. Signal Name Conventions
Description
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
189