MC68HC908AS32A Datasheet, PDF (87/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

BDLC CPU Interface
IMSG — Ignore Message Bit
This bit is used to disable the receiver until a new start-of-frame (SOF) is detected.
1 = Disable receiver. When set, all BDLC interrupt requests will be masked and the status bits will
be held in their reset state. If this bit is set while the BDLC is receiving a message, the rest of
the incoming message will be ignored.
0 = Enable receiver. This bit is cleared automatically by the reception of an SOF symbol or a BREAK
symbol. It will then generate interrupt requests and will allow changes of the status register to
occur. However, these interrupts may still be masked by the interrupt enable (IE) bit.
CLKS — Clock Bit
The nominal BDLC operating frequency (f_BDLC) must always be 1.048576 MHz or 1 MHz for J1850
bus communications to take place. The CLKS register bit allows the user to select the frequency
(1.048576 MHz or 1 MHz) used to adjust symbol timing automatically.
1 = Binary frequency (1.048576 MHz) selected for f_BDLC
0 = Integer frequency (1 MHz) selected for f_BDLC
R1 and R0 — Rate Select Bits
These bits determine the amount by which the frequency of the MCU CGMXCLK signal is divided to
form the MUX interface clock (f_BDLC) which defines the basic timing resolution of the MUX interface.
They may be written only once after reset, after which they become read-only bits.
The nominal frequency of f_BDLC must always be 1.048576 MHz or 1.0 MHz for J1850 bus
communications to take place. Hence, the value programmed into these bits is dependent on the
chosen MCU system clock frequency per Table 4-3.
.
Table 4-3. BDLC Rate Selection
f_XCLK Frequency
1.049 MHz
2.097 MHz
4.194 MHz
8.389 MHz
1.000 MHz
2.000 MHz
4.000 MHz
8.000 MHz
R1 R0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Division
1
2
4
8
1
2
4
8
f_BDLC
1.049 MHz
1.049 MHz
1.049 MHz
1.049 MHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
IE— Interrupt Enable Bit
This bit determines whether the BDLC will generate CPU interrupt requests in run mode. It does not
affect CPU interrupt requests when exiting the BDLC stop or BDLC wait modes. Interrupt requests will
be maintained until all of the interrupt request sources are cleared by performing the specified actions
upon the BDLC’s registers. Interrupts that were pending at the time that this bit is cleared may be lost.
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
If the programmer does not wish to use the interrupt capability of the BDLC, the BDLC state vector
register (BSVR) can be polled periodically by the programmer to determine BDLC states. See 4.6.4
BDLC State Vector Register for a description of the BSVR.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
87