MC68HC908AS32A Datasheet, PDF (243/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

I/O Registers
17.8.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB–MSxA = 0:0) reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0) writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares and the CHxF bit until the low byte (TCHxL) is written.
Register Name and Address
TCH0H — $0027
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Write:
Reset:
Register Name and Address
Bit 7
6
Indeterminate after reset
TCH0L — $0028
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Indeterminate after reset
Register Name and Address
TCH1H — $002A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Write:
Reset:
Indeterminate after reset
Register Name and Address
TCH1L — $002B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Register Name and Address
Bit 7
6
Indeterminate after reset
TCH2H — $002D
5
4
3
2
1
Bit 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Write:
Reset:
Indeterminate after reset
Register Name and Address
TCH2L — $002E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Indeterminate after Reset
Figure 17-9. TIM Channel Registers (TCH0H/L–TCH5H/L)
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
243