MC68HC908AS32A Datasheet, PDF (71/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

BDLC MUX Interface
4.3.1.6 Digital Loopback Mode
When a bus fault has been detected, the digital loopback mode is used to determine if the fault condition
is caused by failure in the node’s internal circuits or elsewhere in the network, including the node’s analog
physical interface. In this mode, the transmit digital output pin (BDTxD) and the receive digital input pin
(BDRxD) of the digital interface are disconnected from the analog physical interface and tied together to
allow the digital portion of the BDLC to transmit and receive its own messages without driving the J1850
bus.
4.3.1.7 Analog Loopback Mode
Analog loopback is used to determine if a bus fault has been caused by a failure in the node’s off-chip
analog transceiver or elsewhere in the network. The BCLD analog loopback mode does not modify the
digital transmit or receive functions of the BDLC. It does, however, ensure that once analog loopback
mode is exited, the BDLC will wait for an idle bus condition before participation in network communication
resumes. If the off-chip analog transceiver has a loopback mode, it usually causes the input to the output
drive stage to be looped back into the receiver, allowing the node to receive messages it has transmitted
without driving the J1850 bus. In this mode, the output to the J1850 bus is typically high impedance. This
allows the communication path through the analog transceiver to be tested without interfering with
network activity. Using the BDLC analog loopback mode in conjunction with the analog transceiver’s
loopback mode ensures that, once the off-chip analog transceiver has exited loopback mode, the BCLD
will not begin communicating before a known condition exists on the J1850 bus.
4.4 BDLC MUX Interface
The MUX interface is responsible for bit encoding/decoding and digital noise filtering between the protocol
handler and the physical interface.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 4-4. BDLC Block Diagram
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
71