MC68HC908AS32A Datasheet, PDF (251/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Monitor Module (MON)
1 µF
1 µF
DB9
2
3
5
V_DD
MC68HC08AS32A
1 _C1+
+
3 _C1–
4 _C2+
+
5 _C2–
7
8
MAX232
V_CC ¹⁶
GND ¹⁵
V+ ²
V– ⁶
10
9
47 pF
V_DD
+
1 µF
1 µF
+
27 pF
4.9152 MHz
1 kΩ
V_DD
1 µF
+
74HC125
6
5
74HC125
2
3
4
10 kΩ
10 k
10 MΩ
9.1 V
RST
OSC2
OSC1
IRQ
PTA0
V_DD
V_DDA
PTC3
PTC0
PTC1
V_SSA
V_SS
1
V_DD
0.1 µF
V_DD
10 k
10 k
10 k
Figure 18-6. Normal Monitor Mode Circuit
18.3.1.1 Monitor Mode Entry
Table 18-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR) and will allow communication provided the pin and clock
conditions are met.
The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the
values on PTC0, PTC1, and PTC3 pins can be changed.
Once out of reset, the MCU waits for the host to send eight security bytes (see 18.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is
ready to receive a command.
18.3.1.2 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code. The COP module is disabled in
monitor mode as long as V_TST, is applied to either the IRQ pin or the RST pin.
Table 18-2 summarizes the differences between user mode and monitor mode regarding vectors.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
251