MC68HC908AS32A Datasheet, PDF (158/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output Ports
Address:
Read:
Write:
Reset:
$0007
Bit 7
0
6
DDRD6
5
DDRD5
0
0
0
= Unimplemented
4
DDRD4
0
3
DDRD3
0
2
DDRD2
0
1
DDRD1
0
Bit 0
DDRD0
0
Figure 13-11. Data Direction Register D (DDRD)
DDRD[6:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD[6:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 13-12 shows the port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDx
READ PTD ($0003)
Figure 13-12. Port D I/O Circuit
When bit DDRDx is a 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a 0,
reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 13-4 summarizes the operation of the port D pins.
Table 13-4. Port D Pin Functions
DDRD
Bit
PTD
Bit
I/O Pin
Mode
Accesses to DDRD
Read/Write
0
X
Input, Hi-Z
DDRD[6:0]
1
X
Output
DDRD[6:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Accesses to PTD
Read
Write
Pin
PTD[6:0]⁽¹⁾
PTD[6:0]
PTD[6:0]⁽¹⁾
MC68HC908AS32A Data Sheet, Rev. 2.0
158
Freescale Semiconductor