MC68HC908AS32A Datasheet, PDF (90/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller (BDLC)
passive, a normalization bit (active) must be generated by the responder and sent prior to its
ID/address byte. When there are multiple responders on the J1850 bus, only one normalization bit is
sent which assists all other transmitting nodes to sync up their response.
TSIFR — Transmit Single Byte IFR with No CRC (Type 1 or 2) Bit
The TSIFR bit is used to request the BDLC to transmit the byte in the BDLC data register (BDR, $003F)
as a single byte IFR with no CRC. Typically, the byte transmitted is a unique identifier or address of
the transmitting (responding) node. See Figure 4-19.
1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol
has been received the BDLC will attempt to transmit the appropriate normalization bit followed
by the byte in the BDR.
0 = The TSIFR bit will be cleared automatically, once the BDLC has successfully transmitted the
byte in the BDR onto the bus, or TEOD is set, or an error is detected on the bus.
HEADER
DATA FIELD
CRC
TYPE 0 — NO IFR
HEADER
DATA FIELD
CRC
NB ID
TYPE 1 — SINGLE BYTE TRANSMITTED FROM A SINGLE RESPONDER
HEADER
DATA FIELD
CRC
NB ID1
ID N
TYPE 2 — SINGLE BYTE TRANSMITTED FROM MULTIPLE RESPONDERS
HEADER
DATA FIELD
CRC
NB
IFR DATA FIELD
CRC
(OPTIONAL)
TYPE 3 — MULTIPLE BYTES TRANSMITTED FROM A SINGLE RESPONDER
NB = Normalization Bit
ID = Identifier (usually the physical address of the responder(s))
HEADER = Specifies one of three frame lengths
Figure 4-19. Types of In-Frame Response (IFR)
If the programmer attempts to set the TSIFR bit immediately after the EOD symbol has been received
from the bus, the TSIFR bit will remain in the reset state and no attempt will be made to transmit the IFR
byte.
If a loss of arbitration occurs when the BDLC attempts to transmit and after the IFR byte winning
arbitration completes transmission, the BDLC will again attempt to transmit the BDR (with no
normalization bit). The BDLC will continue transmission attempts until an error is detected on the bus, or
TEOD is set, or the BDLC transmission is successful.
If loss or arbitration occurs in the last two bits of the IFR byte, two additional 1 bits will not be sent out
because the BDLC will attempt to retransmit the byte in the transmit shift register after the IRF byte
winning arbitration completes transmission.
MC68HC908AS32A Data Sheet, Rev. 2.0
90
Freescale Semiconductor