MC68HC908AS32A Datasheet, PDF (245/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 18
Development Support
18.1 Introduction
This section describes the break module, the monitor read-only memory (MON), and the monitor mode
entry methods.
18.2 Break Module (BRK)
The break module can generate a break interrupt that stops normal program flow at a defined address to
enter a background program.
Features include:
• Accessible I/O registers during break interrupts
• CPU generated break interrupts
• Software generated break interrupts
• COP disabling during break interrupts
18.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal to the SIM. The SIM then causes the CPU to load the instruction register with
a software interrupt instruction (SWI). The program counter vectors to $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode).
These events can cause a break interrupt to occur:
• A CPU generated address (the address in the program counter) matches the contents of the break
address registers.
• Software writes a 1 to the BRKA bit in the break status and control register.
When a CPU generated address matches the contents of the break address registers, the break interrupt
is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and
returns the MCU to normal operation. Figure 18-2 shows the structure of the break module.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
245