MC68HC908AS32A Datasheet, PDF (162/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output Ports
TCH[5:2] — Timer A Channel I/O Bits
The PTF3–PTF0/TCH2 pins are the TIM input capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTF3–PTF0/TCH2 pins are timer channel I/O pins or
general-purpose I/O pins. See 17.8.1 TIM Status and Control Register.
NOTE
Data direction register F (DDRF) does not affect the data direction of port F
pins that are being used by the TIM. However, the DDRF bits always
determine whether reading port F returns the states of the latches or the
states of the pins. See Table 13-6.
13.7.2 Data Direction Register F
Data direction register F determines whether each port F pin is an input or an output. Writing a 1 to a
DDRF bit enables the output buffer for the corresponding port F pin; a 0 disables the output buffer.
Address: $000D
Bit 7
Read: 0
Write:
Reset: 0
6
5
0
0
0
0
= Unimplemented
4
3
2
1
0
DDRF3 DDRF2 DDRF1
0
0
0
0
Figure 13-17. Data Direction Register F (DDRF)
Bit 0
DDRF0
0
DDRF[3:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears DDRF[3:0], configuring all port F pins
as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 13-18 shows the port F I/O logic.
READ DDRF ($000D)
WRITE DDRF ($000D)
RESET
DDRFx
WRITE PTF ($0009)
PTFx
PTFx
READ PTF ($0009)
Figure 13-18. Port F I/O Circuit
MC68HC908AS32A Data Sheet, Rev. 2.0
162
Freescale Semiconductor