MC68HC908AS32A Datasheet, PDF (157/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

13.5 Port D
Port D is an 7-bit general-purpose I/O port.
Port D
13.5.1 Port D Data Register
Port D is a 7-bit special function port that shares seven of its pins with the analog to digital converter and
two with the timer interface modules.
Address: $0003
Bit 7
Read: 0
Write:
Reset:
Alternative Functions:
6
PTD6
ATD14
TCLK
5
PTD5
ATD13
4
3
PTD4
PTD3
Unaffected by Reset
ATD12 ATD11
2
PTD2
ATD10
1
PTD1
ATD9
Bit 0
PTD0
ATD8
= Unimplemented
Figure 13-10. Port D Data Register (PTD)
PTD[6:0] — Port D Data Bits
PTD[6:0] are read/write, software programmable bits. Data direction of PTD[6:0] pins are under the
control of the corresponding bit in data direction register D.
ATD[14:8] — ADC Channel Status Bits
PTD6/ATD14/TCLK–PTD0/ATD8 are seven of the 15 ADC channels. The ADC channel select bits,
CH[4:0], determine whether the PTD6/ATD14/TCLK–PTD0/ATD8 pins are ADC channels or
general-purpose I/O pins. If an ADC channel is selected and a read of this corresponding bit in the port
B data register occurs, the data will be 0 if the data direction for this bit is programmed as an input.
Otherwise, the data will reflect the value in the data latch. See Chapter 3 Analog-to-Digital Converter
(ADC).
Data direction register D (DDRD) does not affect the data direction of port D pins that are being used
by the TIM. However, the DDRD bits always determine whether reading port D returns the states of
the latches or a 0.
TCLK — Timer Clock Input Bit
The PTD6/ATD14/TACLK pin is the external clock input for the timer interface module (TIM). The
prescaler select bits, PS[2:0], select PTD6/ATD14/TACLK as the TIM clock input. See Chapter 17
Timer Interface Module (TIM).
When not selected as the TIM clock, PTD6/ATD14/TACLK is available for general-purpose I/O. While
TCLK is selected corresponding DDRD bits have no effect.
13.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input or an output. Writing a 1 to a
DDRD bit enables the output buffer for the corresponding port D pin; a 0 disables the output buffer.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
157