MC68HC908AS32A Datasheet, PDF (269/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller (BDLC) Characteristics
19.12 Byte Data Link Controller (BDLC) Characteristics
19.12.1 BDLC Transmitter VPW Symbol Timings
Characteristic^{(1), (2)}
Number Symbol
Min
Typ
Max
Unit
Passive logic 0
Passive logic 1
Active logic 0
Active logic 1
Start-of-frame (SOF)
End-of-data (EOD)
End-of-frame (EOF)
Inter-frame separator (IFS)
10
t_TVP1
62
64
66
µs
11
t_TVP2
126
128
130
µs
12
t_TVA1
126
128
130
µs
13
t_TVA2
62
64
66
µs
14
t_TVA3
198
200
202
µs
15
t_TVP3
198
200
202
µs
16
t_TV4
278
280
282
µs
17
t_TV6
298
300
302
µs
1. f_BDLC = 1.048576 or 1.0 MHz, V_DD = 5.0 V ± 10%, V_SS = 0 V
2. See Figure 19-3.
19.12.2 BDLC Receiver VPW Symbol Timings
Characteristic^{(1), (2), (3)}
Number Symbol
Min
Typ
Max
Unit
Passive logic 0
10
t_TRVP1
34
64
96
µs
Passive logic 1
Active logic 0
Active logic 1
11
t_TRVP2
96
12
t_TRVA1
96
13
t_TRVA2
34
128
163
µs
128
163
µs
64
96
µs
Start-of-frame (SOF)
14
t_TRVA3
163
200
239
µs
End-of-data (EOD)
End-of-frame (EOF)
Break
15
t_TRVP3
163
200
239
µs
16
t_TRV4
239
280
320
µs
18
t_TRV6
280
—
—
µs
1. f_BDLC = 1.048576 or 1.0 MHz, V_DD = 5.0 V ± 10%, V_SS = 0 V
2. The receiver symbol timing boundaries are subject to an uncertainty of 1 t_BDLC µs due to sampling considerations.
3. See Figure 19-3.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
269