MC68HC908AS32A Datasheet, PDF (116/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Configuration Register (CONFIG1)
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. Refer to Chapter 11 Low-Voltage Inhibit (LVI).
1 = LVI module resets enabled
0 = LVI module resets disabled
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. Refer to Chapter 11 Low-Voltage Inhibit (LVI).
1 = LVI module power enabled
0 = LVI module power disabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay. Refer to Chapter 15 System Integration Module (SIM).
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE
If using an external crystal oscillator, do not set the SSREC bit.
COPL — COP Long Timeout
COPL enables the shorter COP timeout period. Refer to Chapter 8 Computer Operating Properly
(COP).
1 = COP timeout period is 8176 CGMXCLK cycles
0 = COP timeout period is 262,128 CGMXCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. Refer to Chapter 8 Computer Operating Properly (COP).
1 = COP module disabled
0 = COP module enabled
MC68HC908AS32A Data Sheet, Rev. 2.0
116
Freescale Semiconductor