MC68HC908AS32A Datasheet, PDF (267/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Module Characteristics
19.9.3 CGM Acquisition/Lock Time Information
Description⁽¹⁾
Symbol
Min
Typ⁽²⁾
Max
Unit
Manual mode time to stable⁽³⁾
t_ACQ
—
(8 x V_DDA) /
(f_CGMXCLK x K_ACQ)
—
s
Manual stable to lock time⁽¹⁾
t_AL
—
(4 x V_DDA) /
(f_CGMXCLK x K_TRK)
—
s
Manual acquisition time
t_Lock
—
t_ACQ+t_AL
—
s
Tracking mode entry frequency tolerance
D_TRK
0
—
± 3.6
%
Acquisition mode entry frequency tolerance
D_UNT
± 6.3
—
± 7.2
%
LOCK entry frequency tolerance
D_Lock
0
—
± 0.9
%
LOCK exit frequency tolerance
D_UNL
± 0.9
—
± 1.8
%
Reference cycles per acquisition mode
measurement
n_ACQ
—
32
—
—
Reference cycles per tracking mode
measurement
n_TRK
—
128
—
—
Automatic mode time
to stable⁽¹⁾
t_ACQ
n_ACQ/f_XCLK
(8 x V_DDA) /
(f_XCLK x K_ACQ)
s
Automatic stable to lock time⁽¹⁾
Automatic lock time
PLL jitter, deviation of average bus frequency
over 2 ms⁽⁴⁾
t_AL
t_Lock
n_TRK/f_XCLK
—
0
(4 x V_DDA) /
(f_XCLK x K_TRK)
0.65
—
—
s
25
ms
± (f_CRYS)
%
x (.025%) x (N/4)
K value for automatic mode time to stable
K_ACQ
—
0.2
—
—
K value
K_TRK
—
0.004
—
—
1. V_DD = 5.0 Vdc ± 0.5 V, V_SS = 0 Vdc, T_A = –40C to T_A(MAX), unless otherwise noted.
2. Conditions for typical and maximum values are for run mode with f_CGMXCLK = 8 MHz, f_BUSDES = 8 MHz, N = 4, L = 7,
discharged C_F = 15 nF, V_DD = 5 Vdc.
3. If C_F is chosen correctly.
4. N = VCO frequency multiplied. Guaranteed but not tested. Refer to Chapter 5 Clock Generator Module (CGM) for guidance
on the use of the PLL.
19.10 Timer Module Characteristics
Characteristic
Input capture pulse width
Input clock pulse width
Symbol
t_TIH, t_TIL
t_TCH, t_TCL
Min
125
(1/f_OP) + 5
Max
—
—
Unit
ns
ns
19.11 Memory Characteristics
19.11.1 RAM Memory Characteristics
Characteristic
RAM data retention voltage
Symbol
Min
V_RDR
0.7
Max
—
Unit
V
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
267