MC68HC908AS32A Datasheet, PDF (190/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
M68HC08 CPU
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT (ALU)
CONTROL AND STATUS REGISTERS
USER FLASH — 32, 256 BYTES
USER RAM — 1024 BYTES
USER EEPROM — 512 BYTES
MONITOR ROM — 256 BYTES
USER FLASH VECTOR SPACE — 52 BYTES
OSC1
OSC2
CGMXFC
CLOCK GENERATOR
MODULE
RST
SYSTEM INTEGRATION
MODULE
IRQ
IRQ MODULE
V_REFH
ANALOG-TO-DIGITAL
MODULE
BREAK MODULE
LOW-VOLTAGE INHIBIT
MODULE
COMPUTER OPERATING
PROPERLY MODULE
6-CHANNEL TIMER
INTERFACE MODULE
PROGRAMMABLE INTERRUPT
TIMER MODULE
SERIAL COMMUNICATIONS
INTERFACE MODULE
SERIAL PERIPHERAL
INTERFACE MODULE
BYTE DATA LINK CONTROLLER
PTA7–PTA0
PTB7/ATD7–
PTB0/ATD0
PTC4
PTC3
PTC2/MCLK
PTC1–PTC0
PTD6/ATD14/TCLK
PTD5/ATD13
PTA4/ATD12
PTD3/ATD11–
PTD0/ATD8
PTE7/SPSCK
PTE6/MOSI
PTE5/MISO
PTE4/SS
PTE3/TCH1
PTE2/TCH0
PTE1/RxD
PTE0/TxD
PTF3/TCH5–
PTF0/TCH2
POWER-ON RESET
MODULE
BDRxD
BDTxD
V_SS
V_DD
V_DDA
V_SSA
POWER
AV_SS/V_REFK
V_DDAREF
Figure 15-1. Block Diagram Highlighting SIM Block and Pins
15.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 15-3. This clock can
come from either an external oscillator or from the on-chip phase-lock loop (PLL). See Chapter 5 Clock
Generator Module (CGM).
15.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four. See Chapter 5 Clock Generator Module (CGM).
MC68HC908AS32A Data Sheet, Rev. 2.0
190
Freescale Semiconductor