MC68HC908AS32A Datasheet, PDF (143/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

LVI Interrupts
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the LVI_TRIPF voltage (see
Table 11-1). Reset clears the LVIOUT bit.
Table 11-1. LVIOUT Bit Indication
V_DD
At Level:
V_DD > LVI_TRIPR
V_DD < LVI_TRIPF
LVI_TRIPF < V_DD < LVI_TRIPR
LVIOUT
0
1
Previous value
11.5 LVI Interrupts
The LVI module does not generate interrupt requests.
11.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
11.6.1 Wait Mode
With the LVIPWR bit in the configuration register programmed to 1, the LVI module is active after a WAIT
instruction.
With the LVIRST bit in the configuration register programmed to 1, the LVI module can generate a reset
and bring the MCU out of wait mode.
11.6.2 Stop Mode
With the LVISTOP and LVIPWR bits in the configuration register programmed to a 1, the LVI module will
be active after a STOP instruction. Because CPU clocks are disabled during stop mode, the LVI trip will
generate a reset and bring the MCU out of stop.
With the LVIPWR bit in the configuration register programmed to a 1 and the LVISTOP bit at 0, the LVI
module will be inactive after a STOP instruction.
NOTE
The LVI feature is intended to provide the safe shutdown of the
microcontroller and thus protection of related circuitry prior to any
application V_DD voltage collapsing completely to an unsafe level. It is not
intended that users operate the microcontroller at lower than the specified
operating voltage (V_DD).
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
143