MC68HC908AS32A Datasheet, PDF (142/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
V_DD
LOW V_DD
DETECTOR
LVIPWR
FROM CONFIG1
CPU CLOCK
V_DD > LVI_TRIP = 0
V_DD < LVI_TRIP = 1
STOP MODE
FILTER BYPASS
FROM CONFIG1
LVIRST
LVI RESET
ANLGTRIP
LVISTOP
FROM CONFIG1
LVIOUT
Figure 11-1. LVI Module Block Diagram
11.3.1 Polled LVI Operation
In applications that can operate at V_DD levels below the LVI_TRIPF level, software can monitor V_DD by
polling the LVIOUT bit. In the configuration register, the LVIPWR bit must be at 1 to enable the LVI
module, and the LVIRST bit must be at 0 to disable LVI resets.
11.3.2 Forced Reset Operation
In applications that require V_DD to remain above the LVI_TRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when V_DD falls to the LVI_TRIPF level and remains at or below that level for nine
or more consecutive CPU cycles. In the configuration register, the LVIPWR and LVIRST bits must be at
1 to enable the LVI module and to enable LVI resets.
11.3.3 False Reset Protection
In order for the LVI module to reset the MCU,V_DD must remain at or below the LVI_TRIPF level for nine or
more consecutive CPU cycles. V_DD must be above LVI_TRIPR for only one CPU cycle to bring the MCU out
of reset.
11.4 LVI Status Register
The LVI status register flags V_DD voltages below the LVI_TRIPF level.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-2. LVI Status Register (LVISR)
MC68HC908AS32A Data Sheet, Rev. 2.0
142
Freescale Semiconductor