MC68HC908AS32A Datasheet, PDF (76/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller (BDLC)
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE
≥ 240 µs
(C) BREAK
128 µs
OR
(A) LOGIC 0
128 µs
OR
(B) LOGIC 1
200 µs
(D) START OF FRAME
64 µs
64 µs
200 µs
(E) END OF DATA
ACTIVE
PASSIVE
280 µs
300 µs
20 µs
IDLE > 300 µs
(F) END OF FRAME
(G) INTER-FRAME
SEPARATION
(H) IDLE
Figure 4-7. J1850 VPW Symbols with Nominal Symbol Times
Logic 1
A logic 1 is defined as either:
a. An active-to-passive transition followed by a passive period 128 µs in length, or
b. A passive-to-active transition followed by an active period 64 µs in length
See Figure 4-7(b).
Normalization Bit (NB)
The NB symbol has the same property as a logic 1 or a logic 0. It is only used in IFR message
responses.
Break Signal (BREAK)
The BREAK signal is defined as a passive-to-active transition followed by an active period of at least
240 µs. See Figure 4-7(c).
Start-of-Frame Symbol (SOF)
The SOF symbol is defined as passive-to-active transition followed by an active period 200 µs in length
(see Figure 4-7(d)). This allows the data bytes which follow the SOF symbol to begin with a passive
bit, regardless of whether it is a logic 1 or a logic 0.
End-of-Data Symbol (EOD)
The EOD symbol is defined as an active-to-passive transition followed by a passive period 200 µs in
length (see Figure 4-7(e)).
MC68HC908AS32A Data Sheet, Rev. 2.0
76
Freescale Semiconductor