MC68HC908AS32A Datasheet, PDF (247/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Break Module (BRK)
When the internal address bus matches the value written in the break address registers or when software
writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt timing is:
• When a break address is placed at the address of the instruction opcode, the instruction is not
executed until after completion of the break interrupt routine.
• When a break address is placed at an address of an instruction operand, the instruction is executed
before the break interrupt.
• When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction
is executed.
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can
be generated continuously.
CAUTION
A break address should be placed at the address of the instruction opcode.
When software does not change the break address and clears the BRKA
bit in the first break interrupt routine, the next break interrupt will not be
generated after exiting the interrupt routine even when the internal address
bus matches the value written in the break address registers.
18.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether module status bits can be cleared during the break
state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during
the break state. See 15.7.3 SIM Break Flag Control Register and the Break Interrupts subsection for
each module.
18.2.1.2 TIM During Break Interrupts
A break interrupt stops the timer counter.
18.2.1.3 COP During Break Interrupts
The COP is disabled during a break interrupt when V_TST is present on the RST pin. For V_TST, see 19.5
5.0 Volt DC Electrical Characteristics.
18.2.2 Break Module Registers
Three registers control and monitor operation of the break module:
• Break status and control register (BSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
247