MC68HC908AS32A Datasheet, PDF (231/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
• When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
• When changing to a larger output compare value, enable TIM overflow interrupts and write the new
value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the
current counter overflow period. Writing a larger value in an output compare interrupt routine (at
the end of the current pulse) could cause two output compares to occur in the same counter
overflow period.
17.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
PTE2/TCH0 pin. The TIM channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The output compare value in the TIM channel 0 registers initially controls the output on the PTE2/TCH0
pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control
the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that
control the output are the ones written to last. TSC0 controls and monitors the buffered output compare
function and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the
channel 1 pin, PTE3/TCH1, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the
PTF0/TCH2 pin. The TIM channel registers of the linked pair alternately control the output.
Setting the MS2B bit in TIM channel 2 status and control register (TSC2) links channel 2 and channel 3.
The output compare value in the TIM channel 2 registers initially controls the output on the PTF0/TCH2
pin. Writing to the TIM channel 3 registers enables the TIM channel 3 registers to synchronously control
the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (2 or 3) that
control the output are the ones written to last. TSC2 controls and monitors the buffered output compare
function, and TIM channel 3 status and control register (TSC3) is unused. While the MS2B bit is set, the
channel 3 pin, PTF1/TCH3, is available as a general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered output compare channel whose output appears on the
PTF2/TCH4 pin. The TIM channel registers of the linked pair alternately control the output.
Setting the MS4B bit in TIM channel 4 status and control register (TSC4) links channel 4 and channel 5.
The output compare value in the TIM channel 4 registers initially controls the output on the PTF2/TCH4
pin. Writing to the TIM channel 5 registers enables the TIM channel 5 registers to synchronously control
the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (4 or 5) that
control the output are the ones written to last. TSC4 controls and monitors the buffered output compare
function and TIM channel 5 status and control register (TSC5) is unused. While the MS4B bit is set, the
channel 5 pin, PTF3/TCH5, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
231