MC9S12NE64V1 Datasheet, PDF (64/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 1 MC9S12NE64 Device Overview
1.6.2 Resets
Resets are a subset of the interrupts featured inTable 1-7. The different sources capable of generating a
system reset are summarized in Table 1-8.
1.6.2.1
Reset Summary Table
Table 1-8. Reset Summary
Reset
Power-on reset
External reset
Low-voltage reset
Clock monitor reset
COP watchdog reset
Priority
1
1
1
2
3
Source
CRG module
RESET pin
VREG_PHY module
CRG module
CRG module
Vector
$FFFE, $FFFF
$FFFE, $FFFF
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
1.6.2.2 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. See the
respective module block description chapter for register reset states. See the MEBI block description
chapter for mode-dependent pin configuration of port A, B, E, and K out of reset.
See the PIM block description chapter for reset configurations of all peripheral module ports.
See Table 1-1 for locations of the memories depending on the operating mode after reset.
The RAM array is not automatically initialized out of reset.
1.7 Block Configuration for MC9S12NE64
This section contains information regarding how the modules are implemented on the MC9S12NE64
device.
1.7.1 V_DDR/V_REGEN
On the MC9S12NE64, the V_DDR/V_REGEN pin is used to enable or disable the internal voltage 3.3V to 2.5V
regulator. If this pin is tied low, then V_DD1, V_DD2, V_DDPLL, PHY_VDDRX, PHY_VDDTX, and
PHY_VDDA must be supplied externally.
1.7.2 V_DD1, V_DD2, V_SS1, V_SS2
In both the 112-pin LQFP and the 80-pin TQFP-EP package versions, both internal V_DD and V_SS of the
2.5 V domain are bonded out on two sides of the device as two pin pairs (V_DD1/V_SS1 and V_DD2/V_SS2).
V_DD1 and V_DD2 are connected together internally. V_SS1 and V_SS2 are connected together internally. This
allows systems to employ better supply routing and further decoupling.
MC9S12NE64 Data Sheet, Rev 1.0
64
Freescale Semiconductor