MC9S12NE64V1 Datasheet, PDF (310/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 11 Ethernet Media Access Controller (EMACV1)
11.2.6 MII_RXD[3:0] — MII Receive Data
MII_RXD[3:0] is a receive nibble of data to be transferred from the PHY to the EMAC. The nibble is
synchronized to the rising edge of MII_RXCLK. When MII_RXDV is asserted, the EMAC accepts the
MII_RXD[3:0], and at all other times, MII_RXD[3:0] is ignored. MII_RXD[0] is the least significant bit.
Table 11-2 summarizes the permissible encoding of MII_RXD, MII_RXDV, and MII_RXER, as well as
the specific indication provided by each code. A false carrier indication is ignored by the EMAC.
Table 11-2. Permissible Encoding of MII_RXD, MII_RXDV, and MII_RXER
MII_RXDV
0
0
0
0
0
1
1
MII_RXER
0
1
1
1
1
0
1
MII_RXD[3:0]
0000 through 1111
0000
0001 through 1101
1110
1111
0000 through 1111
0000 through 1111
Indication
Normal interframe
Normal interframe
Reserved
False carrier
Reserved
Normal data reception
Data reception with errors
11.2.7 MII_RXDV — MII Receive Data Valid
When this input signal is asserted, the PHY is indicating that a valid nibble is present on the MII. This
signal remains asserted from the first recovered nibble of the frame through the last nibble. Assertion of
MII_RXDV must start no later than the start frame delimiter (SFD).
11.2.8 MII_RXER — MII Receive Error
When this input signal and MII_RXDV are asserted, the PHY is indicating that a media error has been
detected during the transmission of the current frame. At all other times, MII_RXER is ignored. This
signal transitions synchronously with MII_RXCLK.
11.2.9 MII_CRS — MII Carrier Sense
This input signal is asserted when the transmit or receive medium is in a non-idle state. When de-asserted,
this signal indicates that the medium is in an idle state and a transmission can start. In the event of a
collision, MII_CRS remains asserted through the duration of the collision. In full-duplex mode, this signal
is undefined. This signal is not required to transition synchronously with MII_TXCLK or MII_RXCLK.
11.2.10 MII_COL — MII Collision
This input signal is asserted upon detection of a collision, and remains asserted through the duration of the
collision. In full-duplex mode, this signal is undefined. This signal is not required to transition
synchronously with MII_TXCLK or MII_RXCLK.
MC9S12NE64 Data Sheet, Rev. 1.1
310
Freescale Semiconductor