MC9S12NE64V1 Datasheet, PDF (344/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 11 Ethernet Media Access Controller (EMACV1)
11.4.6.2 Read Operation
To perform a read operation through MII management, the OP field in MCMST must be written to 10 while
the BUSY bit is clear. The PADDR field in MPADR indicates which PHY device is addressed and the
RADDR in MRADR indicates which 16-bit register is read from the PHY device. The MII management
creates an MII management frame and serially shifts it out to the PHY through the MII_MDIO pin. After
the turnaround field, the PHY serially shifts the register data from the PHY to the EMAC through the
MII_MDIO pin. After the read MII management frame operation has completed, the BUSY bit clears, the
MRDATA register is updated, and the MMCIF bit in IEVENT is set. If not masked (MMCIE in IMASK
is set), an MII management transfer complete interrupt is pending while this flag is set.
MDC
MDIO
z
(MAC)
MDIO z
z
(PHY)
32 1s 0 1 1 0 0 1 1 1 0 0 0 0 0 1 z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 ^z
Optional
Preamble
Start
Opcode
(Read)
PHY Address
(PHYAD = 0Eh)
Register Address
(REGAD = 01h)
TA
Register Data
Idle
Figure 11-26. Typical MDC/MDIO Read Operation
11.4.6.3 Write Operation
To perform a write operation through MII management, the OP field in MCMST must be written to 01
while the BUSY bit is clear. The PADDR field in MPADR indicates which PHY device is addressed and
the RADDR bit in MRADR indicates which 16-bit register is read from the PHY device. The MII
management creates an MII management frame and serially shifts it out to the PHY through the
MII_MDIO pin. After the turnaround field, the MWDATA register is serially shifted to the PHY through
the MII_MDIO pin. After the write MII management frame operation has completed, the BUSY bit is
cleared and the MMCIF bit in IEVENT is set. If not masked (MMCIE in IMASK is set), an MII
management transfer complete interrupt is pending while this flag is set.
MDC
MDIO
z
(MAC)
32 1s 0 1 0 1 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ^z
Optional
Preamble
Start
Opcode
(Write)
PHY Address
(PHYAD = 0Eh)
Register Address
(REGAD = 01h)
TA
Register Data
Idle
Figure 11-27. Typical MDC/MDIO Write Operation
11.4.7 Loopback
The MII transmit data stream is internally looped back as an MII receive data stream if the MLB bit is set.
The MII_TXCLK and MII_RXCLK are internally driven from the system clock. MII_RXD is driven from
MII_TXD. MII_RXDV is driven from MII_TXEN. MII_RXER is driven from MII_TXER. The
MC9S12NE64 Data Sheet, Rev. 1.1
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Freescale Semiconductor