MC9S12NE64V1 Datasheet, PDF (133/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Memory Map and Register Descriptions
3.3.2.6.5 Pull Device Enable Register (PERL)
Module Base + $2C
Read:
Write:
Reset:
Bit 7
0
—
6
5
4
PERL6 PERL5 PERL4
1
1
1
= Reserved or unimplemented
3
PERL3
1
2
PERL2
1
1
PERL1
1
Figure 3-43. Port L Pull Device Enable Register (PERL)
Bit 0
PERL0
1
Read:Anytime.
Write:Anytime.
This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or
as output in wired-or (open drain) mode. These bits have no effect if the port is used as push-pull output.
Out of reset a pull-up device is enabled.
PERL[6:0] — Pull Device Enable Port L
1 = Either a pull-up or pull-down device is enabled.
0 = Pull-up or pull-down device is disabled.
3.3.2.6.6 Polarity Select Register (PPSL)
Module Base + $2D
Read:
Write:
Reset:
Bit 7
0
—
6
PPSL6
0
5
PPSL5
0
4
PPSL4
0
3
PPSL3
0
2
PPSL2
0
1
PPSL1
0
Bit 0
PPSL0
0
= Reserved or unimplemented
Figure 3-44. Port L Polarity Select Register (PPSL)
Read:Anytime.
Write:Anytime.
This register selects whether a pull-down or a pull-up device is connected to the pin.
PPSL[6:0] — Pull Select Port L
1 = A pull-down device is connected to the associated port L pin, if enabled by the associated bit in
register PERL and if the port is used as input.
0 = A pull-up device is connected to the associated port L pin, if enabled by the associated bit in
register PERL and if the port is used as input or as wired-or output.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
133