MC9S12NE64V1 Datasheet, PDF (353/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Memory Map and Register Descriptions
Read: Anytime
Write: See each bit description
PHYADD[4:0] — EPHY Address for MII Requests
These bits can be written anytime, but the EPHY address is latched to the MII PHY address register
(MII address 21.4:0) only when the EPHYEN bit transitions from 0 to 1. PHYADD4 is the MSB of
the of the EPHY address.
12.3.2.3 Ethernet Physical Transceiver Status Register (EPHYSR)
Module Base + $2
7
6
5
4
3
2
1
R
0
0
100DIS 10DIS
0
0
0
W
RESET:
0
0
1
1
0
0
0
0
EPHYIF
0
= Unimplemented or Reserved
Figure 12-5. Ethernet Physical Transceiver Status Register (EPHYSR)
Read: Anytime
Write: See bit descriptions
100DIS — EPHY Port 100BASE-TX mode status
This bit is not writable — read only. Output to indicate EPHY port Base100-TX mode status.
1 = EPHY port 100BASE-TX disabled
0 = EPHY port 100BASE-TX enabled
10DIS — EPHY Port 10BASE-T mode status
This bit is not writable. Output to indicate EPHY port 10BASE-T mode status.
1 = EPHY port 10BASE-T disabled
0 = EPHY port 10BASE-T enabled
EPHYIF — EPHY Interrupt Flag
EPHYIF indicates that interrupt conditions have occurred. To clear the interrupt flag, write a 1 to this
bit after reading the interrupt control register via the MII management interface.
1 = EPHY interrupt has occurred
0 = EPHY interrupt has not occurred
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
353