MC9S12NE64V1 Datasheet, PDF (49/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Signal Description
1.2.3.11 PE3 / TAGLO / LSTRB — Port E I/O Pin 3 / Low-Byte Strobe (LSTRB)
PE3 can be used as a general-purpose I/O in all modes and is an input with an active pull-up out of reset.
The pull-up can be turned off by clearing PUPEE in the PUCR register. PE3 can also be configured as a
Low-Byte Strobe (LSTRB). The LSTRB signal is used in write operations, so external low byte writes will
not be possible until this function is enabled. LSTRB can be enabled by setting the LSTRE bit in the PEAR
register. In expanded wide and emulation narrow modes, and while BDM tagging is enabled, the LSTRB
function is multiplexed with the TAGLO function. While enabled, a logic zero on the TAGLO pin at the
falling edge of ECLK will tag the low byte of an instruction word being read into the instruction queue.
PE3 is not available in the 80-pin package version.
1.2.3.12 PE2 / R/W — Port E I/O Pin 2 / Read/Write
PE2 can be used as a general-purpose I/O in all modes and is configured as an input with an active pull-up
out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register. If the read/write
function is required, it must be enabled by setting the RDWE bit in the PEAR register. External writes will
not be possible until the read/write function is enabled. The PE2 pin is not available in the 80-pin package
version.
1.2.3.13 PE1 / IRQ — Port E Input Pin 1 / Maskable Interrupt Pin
PE1 is always an input and can be read anytime. The PE1 pin is also the IRQ input used for requesting an
asynchronous interrupt to the MCU. During reset, the I bit in the condition code register (CCR) is set and
any IRQ interrupt is masked until the I bit is cleared. The IRQ is software programmable to either
falling-edge-sensitive triggering or level-sensitive triggering based on the setting of the IRQE bit in the
IRQCR register. The IRQ is always enabled and configured to level-sensitive triggering out of reset. It can
be disabled by clearing IRQEN bit in the IRQCR register. There is an active pull-up on this pin while in
reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register.
1.2.3.14 PE0 / XIRQ — Port E input Pin 0 / Non-Maskable Interrupt Pin
PE0 is always an input and can be read anytime. The PE0 pin is also the XIRQ input for requesting a
non-maskable asynchronous interrupt to the MCU. During reset, the X bit in the condition code register
(CCR) is set and any XIRQ interrupt is masked until the X bit is cleared. Because the XIRQ input is level
sensitive triggered, it can be connected to a multiple-source wired-OR network. There is an active pull-up
on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE
in the PUCR register.
1.2.3.15 PK7 / ECS / ROMCTL — Port K I/O Pin 7
PK7 is a general-purpose I/O pin. During MCU expanded modes of operation, while the EMK bit in the
MODE register is set to 1, this pin is used as the emulation chip select output (ECS). In expanded modes,
the PK7 pin can be used to determine the reset state of the ROMON bit in the MISC register. At the rising
edge of RESET, the state of the PK7 pin is latched to the ROMON bit. There is an active pull-up on this
pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPKE in the
PUCR register. PK7 is not available in the 80-pin package version.
MC9S12NE64 Data Sheet, Rev 1.0
Freescale Semiconductor
49