MC9S12NE64V1 Datasheet, PDF (352/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 12 Ethernet Physical Transceiver (EPHYV2)
ANDIS — Auto Negotiation Disable
This bit can be written anytime, but the value is latched in the ANE bit of the MII PHY control register
(MII address 0.12) only when the EPHYEN bit transitions from 0 to 1.
1 = Auto negotiation is disabled after start-up. A 0 is latched in the ANE bit of the MII PHY control
register (MII address 0.12), and upon completion of the start-up delay (t_Start-up), the EPHY will
bypass auto-negotiation. The mode of operation will be determined by the manual setting of
MII registers.
0 = Auto negotiation is enabled after start-up. A 1 is latched in the ANE bit of the MII PHY control
register (MII address 0.12), and upon completion of the start-up delay (t_Start-up), the EPHY will
enter auto-negotiation. The mode of operation will be automatically determined.
DIS100 — Disable 100 BASE-TX PLL
This bit can be written anytime. Allows user to power down the clock generation PLL for
100BASE-TX clocks.
1 = Disables 100BASE-TX PLL
0 = 100BASE-TX PLL state determined by EPHY operation mode
DIS10 — Disable 10BASE-T PLL
This bit can be written anytime. Allows user to power down the clock generation PLL for 10BASE-T
clocks.
1 = Disables 10BASE-T PLL
0 = 10 BASE-T PLL state determined by EPHY operation mode
LEDEN — LED Drive Enable
This bit can be written anytime.
1 = Enables the EPHY to drive LED signals.
0 = Disables the EPHY to drive LED signals.
EPHYWAI — EPHY Module Stops While in Wait
This bit can be written anytime.
1 = Disables the EPHY module while the MCU is in wait mode. EPHY interrupts cannot be used
to bring the MCU out of wait.
0 = Allows the EPHY module to continue running during wait.
EPHYIEN — EPHY Interrupt Enable
This bit can be written anytime.
1 = Enables EPHY module interrupts
0 = Disables EPHY module interrupts
12.3.2.2 Ethernet Physical Transceiver Control Register 1 (EPHYCTL1)
Module Base + $1
7
6
R
0
0
W
RESET:
0
0
5
4
3
2
1
0
0
PHYADD4 PHYADD3 PHYADD2 PHYADD1 PHYADD0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-4. Ethernet Physical Transceiver Control Register 1 (EPHYCTL1)
MC9S12NE64 Data Sheet, Rev. 1.1
352
Freescale Semiconductor