MC9S12NE64V1 Datasheet, PDF (190/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 6 Timer Module (TIM16B4CV1)
R
W
Reset
7
TCNT7
0
6
TCNT6
5
TCNT5
4
TCNT4
3
TCNT3
2
TCNT2
0
0
0
0
0
Figure 6-11. Timer Count Register Low (TCNTL)
1
TCNT1
0
0
TCNT0
0
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
Read: Anytime
Write: Has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1).
The period of the first count after a write to the TCNT registers may be a different size because the write
is not synchronized with the prescaler clock.
6.3.2.6 Timer System Control Register 1 (TSCR1)
7
6
5
4
3
2
1
0
R
0
0
0
0
TEN
TSWAI
TSFRZ
TFFCA
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-12. Timer System Control Register 1 (TSCR2)
Read: Anytime
Write: Anytime
Table 6-6. TSCR1 Field Descriptions
Field
7
TEN
6
TSWAI
Description
Timer Enable
0 Disables the main timer, including the counter. Can be used for reducing power consumption.
1 Allows the timer to function normally.
If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator because the ÷64 is
generated by the timer prescaler.
Timer Module Stops While in Wait
0 Allows the timer module to continue running during wait.
1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU
out of wait.
TSWAI also affects pulse accumulator.
MC9S12NE64 Data Sheet, Rev. 1.1
190
Freescale Semiconductor