MC9S12NE64V1 Datasheet, PDF (215/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Field
1
ASCIE
0
ASCIF
Memory Map and Register Definition
Table 7-5. ATDCTL2 Field Descriptions (continued)
Description
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Interrupt will be requested whenever ASCIF = 1 is set.
ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see
Section 7.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect.
0 No ATD interrupt occurred
1 ATD sequence complete interrupt pending
Table 7-6. External Trigger Configurations
ETRIGLE
0
0
1
1
ETRIGP
0
1
0
1
External Trigger Sensitivity
Falling edge
Rising edge
Low level
High level
7.3.2.4 ATD Control Register 3 (ATDCTL3)
This register controls the conversion sequence length, FIFO for results registers and behavior in freeze
mode. Writes to this register will abort current conversion sequence but will not start a new sequence.
7
R
0
W
6
S8C
5
S4C
4
S2C
Reset
0
0
0
0
= Unimplemented or Reserved
3
S1C
0
2
FIFO
0
Figure 7-6. ATD Control Register 3 (ATDCTL3)
1
FRZ1
0
0
FRZ0
0
Read: Anytime
Write: Anytime
Table 7-7. ATDCTL3 Field Descriptions
Field
Description
6–3
Conversion Sequence Length — These bits control the number of conversions per sequence. Table 7-8 shows
S8C, S4C, all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12
S2C, S1C Family.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
215