MC9S12NE64V1 Datasheet, PDF (314/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 11 Ethernet Media Access Controller (EMACV1)
While this bit is clear, the EMAC is configured for the internal PHY, all the EMAC MII I/O pins are
not available externally, and the MII interface to the internal PHY is available.
1 = External PHY.
0 = Internal PHY.
NOTE
If MLB is set, EXTPHY is ignored. If EXTPHY is set, it is recommended
that any internal PHY be disabled.
MLB — MAC Loopback
This bit can be written once after a hardware or software reset, but the user must not change this bit
while EMACE or BUSY is set.
While this bit is set, the EMAC is in the loopback mode which routes all transmit traffic to the receiver
and disables the MII.
1 = Loopback mode.
0 = Normal operation.
NOTE
While configured for loopback mode, receiver frame recognition algorithms
remain active and transmitted frames failing to meet acceptance criteria will
be dropped by the receiver.
FDX — Full Duplex
This bit can be written anytime, but the user must not modify this bit while EMACE is set.
While this bit is set, the EMAC is set for full-duplex mode, which bypasses the carrier sense multiple
access with collision detect (CSMA/CD) protocol. Frame reception occurs independently of frame
transmission.
While this bit is clear, the EMAC is set for half-duplex mode. Frame reception is disabled during frame
transmission. The mode used is the traditional mode of operation that relies on the CSMA/CD protocol
to manage collisions and network access.
1 = Full-duplex mode.
0 = Half-duplex mode.
11.3.2.2 Receive Control and Status (RXCTS)
Module Base + $3
7
6
R
RXACT
0
W
RESET:
0
0
5
4
3
0
RFCE
0
0
0
0
2
PROM
0
1
CONMC
0
0
BCREJ
0
= Unimplemented or Reserved
Figure 11-3. Receive Control and Status (RXCTS)
Read: Anytime.
Write: See each bit description.
MC9S12NE64 Data Sheet, Rev. 1.1
314
Freescale Semiconductor