MC9S12NE64V1 Datasheet, PDF (113/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

3.3.2.1 Port T Registers
Memory Map and Register Descriptions
3.3.2.1.1 I/O Register (PTT)
Module Base + $0
Bit 7
6
5
4
3
2
1
Bit 0
Read: _PTT7
PTT6
PTT5
PTT4
0
0
0
0
Write
TIM
IOC7
IOC6
IOC5
IOC4
Reset:
0
0
0
0
—
—
—
—
= Reserved or unimplemented
Figure 3-2. Port T I/O Register (PTT)
Read:Anytime.
Write:Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The standard timer module (TIM) can be configured to use the PT[7:4] as timer input capture/output
compare pins. If IOC[7:4]-channel is defined as output, the related port T is assigned to IOC function.
3.3.2.1.2 Input Register (PTIT)
Module Base + $1
Bit 7
6
5
4
3
2
1
Bit 0
Read: PTIT7
PTIT6
PTIT5
PTIT4
0
0
0
0
Write:
Reset:
—
—
—
—
—
—
—
—
= Reserved or unimplemented
Figure 3-3. Port T Input Register (PTIT)
Read:Anytime.
Write:Never, writes to this register have no effect.
This register always reads back the status of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
3.3.2.1.3 Data Direction Register (DDRT)
Module Base + $2
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
Write: ^{DDRT7 DDRT6 DDRT5 DDRT4}
Reset:
0
0
0
0
—
—
—
—
= Reserved or unimplemented
Figure 3-4. Port T Data Direction Register (DDRT)
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
113