MC9S12NE64V1 Datasheet, PDF (402/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 15 Multiplexed External Bus Interface (MEBIV3)
15.3.2.3 Data Direction Register A (DDRA)
R
W
Reset
7
Bit 7
0
6
5
4
3
2
6
5
4
3
2
0
0
0
0
0
Figure 15-4. Data Direction Register A (DDRA)
1
0
1
Bit 0
0
0
Read: Anytime when register is in the map
Write: Anytime when register is in the map
This register controls the data direction for port A. When port A is operating as a general-purpose I/O port,
DDRA determines the primary direction for each port A pin. A 1 causes the associated port pin to be an
output and a 0 causes the associated pin to be a high-impedance input. The value in a DDR bit also affects
the source of data for reads of the corresponding PORTA register. If the DDR bit is 0 (input) the buffered
pin input state is read. If the DDR bit is 1 (output) the associated port data register bit state is read.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally. It is reset to 0x00 so the DDR does not override the three-state control
signals.
Table 15-3. DDRA Field Descriptions
Field
7:0
DDRA
Description
Data Direction Port A
0 Configure the corresponding I/O pin as an input
1 Configure the corresponding I/O pin as an output
MC9S12NE64 Data Sheet, Rev. 1.1
402
Freescale Semiconductor