MC9S12NE64V1 Datasheet, PDF (116/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 3 Port Integration Module (PIM9NE64V1)
3.3.2.2 Port S Registers
3.3.2.2.1 I/O Register (PTS)
Module Base + $8
Read:
Write:
SPI
SCI
Reset:
Bit 7
PTS7
SS
—
0
6
PTS6
SCK
—
0
5
PTS5
MOSI
—
0
4
PTS4
MISO
—
0
3
2
1
Bit 0
PTS3
PTS2
PTS1
PTS0
—
—
—
—
SCI1_TXD SCI1_RXD SCI0_TXD SCI0_RXD
0
0
0
0
Figure 3-8. Port S I/O Register (PTS)
Read:Anytime.
Write:Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The SPI function takes precedence over the general-purpose I/O function if the SPI module is enabled. If
the SPI is enabled the PS[7:4] pins become SPI_SS, SPI_SCK, SPI_MOSI, and SPI_MISO, and their
configuration is determined by several status bits in the SPI module. Refer to the SPI block description
chapter for details.
The SCI1 and SCI0 function take precedence over the general-purpose I/O function on pins PS[3:0]. If the
SCI1 or SCI0 transmitters or receivers are enabled, the SCI1 and SCI0 transmit pins, SCI1_TXD and
SCI0_TXD, are configured as outputs if the corresponding transmitter is enabled. The SCI1 and SCI0
receive pins, SCI1_RXD and SCI0_RXD, are configured as inputs if the corresponding receiver is enabled.
Refer to the SCI block description chapter for details.
3.3.2.2.2 Input Register (PTIS)
Module Base + $9
Read:
Write:
Reset:
Bit 7
PTIS7
—
6
PTIS6
—
5
PTIS5
—
4
PTIS4
—
3
PTIS3
—
2
PTIS2
—
1
PTIS1
—
Bit 0
PTIS0
—
= Reserved or unimplemented
Figure 3-9. Port S Input Register (PTIS)
Read:Anytime.
Write: writes to this register have no effect.
This register always reads back the status of the associated pins. This also can be used to detect overload
or short circuit conditions on output pins.
MC9S12NE64 Data Sheet, Rev. 1.1
116
Freescale Semiconductor